Senior RTL Design Engineer — Verilog, Synthesis

A leading technology company based in Canada seeks an experienced digital designer to support and debug RTL designs. Ideal candidates should have expertise in Verilog or System Verilog, as well as knowledge of LINT, CDC, and RDC tools. The role offers a competitive salary between CAD 77,000 and CAD 120,000, and embraces a flexible working model adapting to US time zones. The organization values diversity and provides an inclusive workplace for all employees.

#J-18808-Ljbffr