Engineering Intern - Design Verification, Neural Engine (Spring 2027 Co-op)

Rivian internships are experiences optimized for student candidates. To be eligible, you must be an undergraduate or graduate student in an accredited program during the internship term with an expected graduation date between December 2027 and 2029. Rivian's Internship Program requires active student enrollment. Information regarding your expected degree completion date is collected solely to verify eligibility and determine your availability for future full-time opportunities. Rivian is an equal opportunity employer and does not use graduation dates to determine the age of applicants or as a basis for discriminatory hiring decisions.

If you are not pursuing a degree, please see our full time positions on our Rivian careers site. Note that if your university has specific requirements for internship programs, it is your responsibility to fulfill those requirements.

Our Spring Co-op program runs from Jan-Aug 2027. In order to be considered for this role, you must be available to work onsite, full time (40 hours per week), for the entire duration. If you're unable to work during the spring semester, please instead apply to our Summer Internship Program.

In this role, you will evaluate methodologies for development of Neural Engine Silicon with focus on performance, power and functional safety. Work on AI based tools and setting up new infrastructure and flows for ADAS Silicon development.

Experiment with AI tools for Silicon development: Leverage LLMs and generative agents to automate RTL generation, code documentation, and bug localization within the DLA (Deep Learning Accelerator) pipeline.

Understand system architecture and develop tools for performance modeling and testing: Build bit-accurate C++/SystemC models to validate the throughput of neural network layers against "golden" ML frameworks like PyTorch.

Develop tools and verification collateral for large-scale ASIC development: Create scalable UVM-based testbench components and automated regression scripts to support high-complexity SoC integration.

Interconnect & Latency Analysis: Architect and implement performance monitors for Interconnect/AXI interfaces to analyze how on chip network impacts real-time inference latency.

Safety-Aware Verification & Fault Injection: Design automated verification collateral to simulate hardware-level faults, ensuring that safety mechanisms correctly detect errors according to ISO 26262 automotive standards.

Must be currently pursuing a bachelors, masters, or PhD degree at an accredited university

Actively pursuing a degree or one closely related in Electrical or Computer Engineering

Fundamentals of Computer architecture

CPU and Memory hierarchy

C/Python coding skills

* System verilog language

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