Fellow - Pre-Silicon Verification - Quality and Methodology

Overview

**WHAT YOU DO AT AMD CHANGES EVERYTHING**

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. **Together, we advance your career.**

Responsibilities

**THE ROLE:**

AMD is seeking a Fellow-level Pre-Silicon Verification Quality and Methodology to define, elevate, and scale best-in-class verification across high-impact silicon programs within a mixed-signal IP organization providing a portfolio of IP to the entire AMD product portfolio.

You will shape verification architecture, methodology, automation strategy, AI enablement, and technical direction across multiple product domains. You will influence roadmaps, mentor senior DV leaders, and ensure that verification quality and predictability scale with AMD’s growing silicon complexity.

This is an opportunity to leave a lasting technical fingerprint on AMD’s next generation of products.

**KEY RESPONSIBILITIES:**

**Verification Architecture**

• Define scalable mixed-signal verification architectures for advanced analog-digital subsystems.
• Establish signoff criteria, coverage models, and closure frameworks across concurrent silicon programs.
• Integrate digital UVM-based environments with analog/mixed-signal modeling strategies (real-number modeling, AMS co-simulation, abstraction frameworks).

**Technical Strategy**

• Set long-term DV methodology direction across the teams and organization.
• Modernize regression, debug, and coverage analytics infrastructure.
• Define AI-assisted verification strategy (intelligent test generation, regression triage, coverage gap prediction).

**Organizational Elevation**

• Mentor senior DV architects and regional leads.
• Standardize methodology across global teams.
• Lead technical risk reviews and drive silicon escape reduction at systemic scale.

**Industry Influence**

• Represent AMD in technical forums and standards bodies.
• Contribute thought leadership in advanced mixed-signal verification.

**PREFERRED EXPERIENCE:**

• 20+ years leading complex pre-silicon verification efforts.
• Deep expertise in mixed-signal DV methodologies, including:

+ System Verilog / UVM

+ Real-number modeling (RNM)

+ AMS co-simulation flows

+ Coverage-driven closure for analog/digital interaction

+ Formal and hybrid verification strategies

• Experience architecting verification for mixed-signal IP & complex subsystems.
• Proven ability to scale verification across geographically distributed teams.
• Recognized as a technical authority within your organization or industry.

**ACADEMIC CREDENTIALS:**

• Bachelors or Masters degree in computer engineering/Electrical Engineering

**LOCATION**: Santa Clara, CA ( Open to All AMD location)

#LI-SL3

#LI-HYBRID

**This role is not eligible for visa sponsorship.**

Qualifications

*Benefits offered are described:* AMD benefits at a glance.

*AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.*

*AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available* *here.*

*This posting is for an existing vacancy.*